Skills Built:Binary/Hex ConversionTwo's Complement ArithmeticBCD & Gray Code EncodingParity Bit Error Detection

1. Intuition First: Why Binary & The Odometer Model

Physical computers do not operate on decimal digits because transistors are electronic switches. An analog voltage that continuously slides between $0\text{ V}$ and $5\text{ V}$ is vulnerable to thermal noise, supply ripple, and component aging. By dividing voltages into two distinct noise-tolerant zones—LOW ( $0$ ) and HIGH ( $1$ )—digital logic achieves near-perfect signal restoration across millions of cascading logic gates.

The Rolling Odometer Analogy

Think of a mechanical car odometer. Each dial contains ten numerals ( $0$ through $9$ ). When a wheel passes $9$ , it cannot display $10$ in a single slot; it rolls back to $0$ and mechanical teeth physically push the wheel immediately to its left forward by one increment.

Binary arithmetic functions identically, except each wheel only has two symbols: $0$ and $1$ :

Counting starts at $0_2$ .
The next increment is $1_2$ .
Adding another count forces a rollover: the slot resets to $0$ and generates a carry to the next column, yielding $10_2$ (decimal $2$ ).

Decimal odometer rollover:  09 -> 10 -> ... -> 99 -> 100
Binary counter rollover:    01 -> 10 -> ... -> 11 -> 100

Two's Complement: The Odometer Running in Reverse

What happens if a brand new car with $000000$ on the odometer rolls backwards by one kilometer? The dials roll backwards past zero to display $999999$ . In mechanical systems, everyone intuitively understands that $999999$ represents $-1$ .

In an $8$ -bit digital register, counting down backwards from 0000 0000 similarly wraps around to 1111 1111. Two's complement arithmetic uses this exact ring topology:

Unsigned representation views 1111 1111 as $255$ .
Signed representation views 1111 1111 as $-1$ .

Because addition and subtraction follow identical modular bitwise mechanics regardless of sign, digital ALUs can execute subtraction using simple adder hardware without separate subtractor circuits.

2. Formula & Unit Quick-Reference Strip

Formula & Unit Quick-Reference Strip

Radix ExpansionDimensionless

N = \sum_{i=-m}^{n-1} d_i \cdot r^i

Positional value of any digit string with radix r, n integer digits, and m fractional digits.

Bit CapacityBits

b = \lceil \log_2 N \rceil

Minimum bit width required to encode N distinct binary states or decimal values.

Two's ComplementModulo 2^n

-x \equiv \bar{x} + 1 \pmod{2^n}

Negating a signed number: invert every bit (one's complement) and add 1.

Signed Range (n-bit)Integer

-2^{n-1} \le x \le 2^{n-1} - 1

Two's complement dynamic range. For 8 bits: -128 to +127.

Unsigned Range (n-bit)Integer

0 \le x \le 2^n - 1

Unsigned integer dynamic range. For 8 bits: 0 to 255.

Even Parity BitBit (0 or 1)

P = b_{n-1} \oplus \dots \oplus b_0

XOR sum of data bits ensuring total number of 1s in transmitted frame is even.

3. Mathematical Derivation: Two's Complement Negation & Overflow

4. Typical Bench Values & Standard Register Widths

Digital hardware architectures enforce standardized register widths and word sizes:

Typical Laboratory Hardware Ranges

Parameter / Part	Typical Value	Lab Range	Practical Notes
8-bit Byte (uint8_t / int8_t)	0 to 255 (Unsigned)	-128 to +127 (Signed)	Fundamental addressable memory byte in AVR, 8051, and x86 architectures
16-bit Half-Word (uint16_t)	0 to 65,535	-32,768 to +32,767	Standard 16-bit timer capture registers and high-resolution ADC channels
BCD Nibble (4-bit)	0000 to 1001 (0 to 9 dec)	1010 to 1111 illegal	Real-time clocks (DS3231/DS1307) and dual-slope DMM display controllers
TTL Logic Thresholds	LOW ≤ 0.8V, HIGH ≥ 2.0V	0V to 5.0V DC rail	Guaranteed 400mV noise margin in standard 74LS series ICs

5. Worked Engineering Problems

Problem 1: Mixed Radix Conversion (Integer & Fractional)

Step-by-Step Worked Problem

Convert the decimal value 156.625 into its equivalent binary and hexadecimal representations.

Step 1: Convert Integer Part (156) to Binary

Decompose 156 into powers of 2: 156 = 128 + 16 + 8 + 4 = 2^7 + 2^4 + 2^3 + 2^2. Placing 1s in positions 7, 4, 3, 2 and 0s elsewhere gives: (156)_10 = 1001 1100_2.

Step 2: Convert Fractional Part (0.625) to Binary

Decompose into negative powers of 2: 0.625 = 0.5 + 0.125 = 2^(-1) + 2^(-3). Placing 1s in the tenths (2^-1) and thousandths (2^-3) fractional positions gives: (0.625)_10 = 0.101_2.

Step 3: Combine and Group for Hexadecimal

Full binary: 1001 1100.101_2. Group into 4-bit nibbles outward from the binary point: Integer: (1001)_2 = 9, (1100)_2 = C. Fraction: (1010)_2 = A (pad with a trailing zero!).

Problem 2: Two's Complement Subtraction

Step-by-Step Worked Problem

Compute (25 - 42) using 8-bit two's complement arithmetic. Show the step-by-step negation, addition, and decimal verification.

Step 1: Binary Representation of Operands

Express positive values in 8-bit binary: +25 = 0001 1001_2, +42 = 0010 1010_2.

Step 2: Form Two's Complement of the Subtrahend (-42)

Take one's complement of +42: ~0010 1010 = 1101 0101. Add 1: 1101 0101 + 1 = 1101 0110_2. Thus, -42 = 1101 0110_2.

Step 3: Perform Binary Addition (25 + (-42))

Add the two 8-bit words: 0001 1001 (+25) + 1101 0110 (-42) = 1110 1111_2. Notice there is no carry-out from the MSB.

Step 4: Decode and Verify Result

The MSB is 1, indicating a negative result. To find its magnitude, invert and add 1: ~1110 1111 = 0001 0000; 0001 0000 + 1 = 0001 0001_2 = 17_10. Therefore, the result represents -17.

Problem 3: Signed Addition & Hardware Overflow Detection

Step-by-Step Worked Problem

In an 8-bit ALU register, add (+100) and (+60). Determine the resulting binary word, interpret it as a signed integer, and verify whether arithmetic overflow occurred.

Step 1: Convert Operands to 8-bit Two's Complement

+100 = 64 + 32 + 4 = 0110 0100_2. +60 = 32 + 16 + 8 + 4 = 0011 1100_2.

Step 2: Compute Binary Addition

0110 0100 (+100) + 0011 1100 (+60): Column 6 carry generates a carry into bit 7: C_in = 1. Bit 7 addition: 0 + 0 + C_in = 1 with carry-out C_out = 0. Resulting word: 1010 0000_2.

Step 3: Interpret Result and Evaluate Overflow Condition

1010 0000 has MSB = 1, so the circuit evaluates it as negative: -128 + 32 = -96! Adding two positive quantities (+100 + +60 = +160) resulted in a negative value because +160 exceeds the maximum 8-bit signed positive limit (+127). Hardware overflow flag: V = C_in XOR C_out = 1 XOR 0 = 1 (Overflow Flag Set).

6. Common Exam Traps & Where Marks Are Lost

Common Exam Traps & Where Marks Are Lost

Avoid these classic calculation errors frequently spotted on semester examination answer scripts:

Reading 1111 1111 as 255 when the problem specifies signed integers. In signed two's complement, 1111 1111 is -1. Only interpret it as 255 if the question explicitly states unsigned.
Forgetting that the most negative number has no positive partner: In 8-bit two's complement, -128 is 1000 0000. Negating it (~1000 0000 + 1 = 0111 1111 + 1 = 1000 0000) yields -128 again because +128 cannot fit in 8 bits.
Reading BCD as plain binary: 1001 0101 in BCD is 95 decimal (1001 = 9, 0101 = 5). Interpreting it as straight binary gives 128 + 16 + 4 + 1 = 149, which is completely incorrect.
Grouping binary fractions from the left: When grouping a fractional binary number into hex nibbles, you MUST group to the right starting from the binary point and pad zeros on the trailing right (e.g., 0.101 becomes 0.1010 = 0.A, not 0.5).
Using sign-magnitude for negative numbers when two's complement is requested: -5 in sign-magnitude is 1000 0101, whereas in two's complement it is 1111 1011. Modern microprocessors exclusively use two's complement.

7. Interactive Simulator & 'Try Breaking It'

Experiment with binary bit patterns, carry generation, and logic gates in the interactive circuit simulator below:

Interactive Engineering Simulator

logic-gates

Simulator will mount when scrolled into view (conserving CPU & memory)

Try Breaking It: Predict Before You Test

Set 0111 1111 (+127), predict the signed reading, then add 1.

8. Parametrised Practice Problem

Solidify your conversion mastery with randomized parameter sets:

Parametrised Practice Problem

Thévenin Equivalent of a Loaded Voltage Divider

A 12 V DC voltage source powers a divider with R1 = 20 Ω and R2 = 20 Ω. Calculate the open-circuit Thévenin voltage V_th (in Volts) appearing across terminals of R2.

Progressive Hints:

9. Unit Mastery Quiz

5-Question Mastery Check

Unit Quiz: Number Systems, Codes and Binary Arithmetic

Q1.What is the hexadecimal representation of the 8-bit binary word 1101 0110?

Q2.What is decimal -5 represented in 8-bit two's complement notation?

Q3.What is the valid numerical range of a 6-bit signed two's complement integer?

Q4.What is the Gray code equivalent of the binary number 1011?

Q5.What is the decimal equivalent of the Binary Coded Decimal (BCD) word 0111 0010?

0 of 5 answered