EEE Circuit Analysis & Laboratory Workbench
Live Build
Working System & Interface Capture
Topology
System Schematic & Architecture
Telemetry & Bench
Additional Working Interface & Simulator Captures
Overview
A rigorous empirical record of physical circuit implementations across analog components, power rectification, active filtering, and oscilloscope probing conducted through lab experiments and self-directed bench investigations.
The Problem
Theoretical circuit equations frequently diverge from real-world bench behavior due to component tolerances (±5% resistors, ±20% electrolytic capacitors), parasitic capacitances, and oscilloscope probe loading effects.
The Solution
Documented practical bench procedures, 10X probe compensation techniques, star-grounding to suppress 50Hz mains hum, and comparative error analysis between theoretical nodal calculations and physical DSO measurements.
Key Features
Engineering Obstacles
Challenges Overcome
1X probe loading introduced 100pF parallel capacitance, artificially rolling off amplifier gain above 80kHz. Solved by switching to 10X attenuation probes (15pF loading).
High-gain LM741 circuits picked up 180mV of 50Hz mains hum from bench AC ground loops. Resolved via star grounding and shortening scope ground leads.
Verification & Impact
Results & Verification
Filter cutoff frequency matched theoretical calculations within 0.7% error (1.58 kHz measured vs 1.591 kHz theoretical).
Rectifier ripple voltage matched theoretical formula Vr = I / (2 f C) within 8.5% across multiple reservoir capacitor values.
All prescribed university laboratory modules verified with documented waveforms and faculty verification.